About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• This position at Marvell involves spearheading enhancements and providing critical support for our sophisticated Place and Route Flow, seamlessly incorporating industry-standard EDA tools.

• Your responsibilities encompass conducting in-depth timing analysis and closure on multiple complex and expert-level logic blocks, multi-hierarchy fullchip constraint and timing closure, and multi-hierarchy constraint development.

• You will be at the forefront of developing and implementing intricate timing and logic ECOs.

• Collaboration is key, and you will work closely with the RTL design team to drive modifications that effectively resolve congestion and timing issues.

• Engaging with the global timing team, your role extends to debugging and resolving block-level timing issues observed at the partition level or full chip.

• Moreover, your influence will extend to interactions with tool vendors, where you'll drive improvements and conduct evaluations of new tools and functions. Customer interaction and collaboration is a plus.

• This role presents an exciting opportunity for seasoned engineers to contribute to cutting-edge projects in a collaborative and innovative environment at Marvell.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

• Strong understanding of standard RTL to GDS flows and methodology

• Strong knowledge of Primetime. Hyperscale is a plus.

• Proficient in Synopsys Design Constraints (SDC) to create and debug constraints.

• Proficient in writing timing ECOs for Cadence Innovus

• Deep understanding on how clocking structures, IP complexities, DRVs, and Power and Signal Integrity affects timing

• Understanding of DFT structures. Tessent a plus.

• Worked on 3/5/7nm technologies.

• Proficient in a scripting language (Python, Perl)

• Work with a worldwide team to coordinate timing closure

• Communicate clearly and efficiently through messaging app, emails, and meetings

• Good communication skills and self-discipline contributing in a team environment

#LI-TM1

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.