At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.
The OpportunityAs a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow.
The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
* Develop and maintain leading-edge P&R flows addressing the needs of Marvell's various Business Units
* Contribute to the deployment and support of these flows
* Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform
* Come-up with innovative solutions to ever-increasing design challenges
* Keep up with process and tool evolutions
* Interface with EDA vendors for optimal tool usage.
* Bachelor's degree in Computer Science, Electrical Engineering or related fields and 8-10 years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-8 years of experience.
* 2+ years of recent experience with Cadence Innovus.
* Proven experience with advance nodes 7nm or below tape out. Familiar with Finfet, Dual Patterning and ULV challenges.
* Solid understanding, at least at block level but preferably at SoC level of:
o timing closure issues and ways to debug and fix them.
o floorplanning and routability issues and ways to fix them
o Power Grid design and validation.
o Various Clock synthesis schemes.
o SI, EM/IR, complex DRC rules
o Power intent and Multiple power domains implementation.
o High speed and low power implementation techniques/trade-offs.
o Upstream/Downstream flow correlation.
* Good level of proficiency in Tcl scripting in the context of flow development.
* Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking
* Team player with good verbal and written communication skills.
* Ability to run the following tasks is a plus:
o gate-to-gate equivalence checking
o Parasitic Extraction
o Physical Verification (at least DRC)
o Early Rail Analysis
* Experience with implementation exploration methods
* Experience with EDA tool benchmarksThe Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.